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CY62167EV18 mobl ? 16-mbit (1m x 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05447 rev. *e revised august 16, 2007 features very high speed: 55 ns wide voltage range: 1.65v ? 2.25v ultra low standby power ? typical standby current: 1.5 a ? maximum standby current: 12 a ultra low active power ? typical active current: 2.2 ma @ f = 1 mhz easy memory expansion with ce 1 , ce 2 , and oe features automatic power down when deselected cmos for optimum speed and power offered in pb-free 48-ball vfbga packages functional description the CY62167EV18 is a high performance cmos static ram organized as 1m words by 16 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature th at reduces power consumption by 99% when addresses are not toggling. place the device into standby mode when deselected (ce 1 high or ce 2 low or both bhe and ble are high). the input and output pins (io 0 through io 15 ) are placed in a high impedance state when: the device is deselected (ce 1 high or ce 2 low); outputs are disabled (oe high); both byte high enable and byte low enable are disabled (bhe , ble high); and a write operation is in progress (ce 1 low, ce 2 high and we low). to write to the device, take chip enables (ce 1 low and ce 2 high) and write enable (we ) input low. if byte low enable (ble ) is low, then data from io pins (io 0 through io 7 ) is written into the location specified on the address pins (a 0 through a 19 ). if byte high enable (bhe ) is low, then data from io pins (io 8 through io 15 ) is written into the location specified on the address pins (a 0 through a 19 ). to read from the device , take chip enables (ce 1 low and ce 2 high) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appears on io 0 to io 7 . if byte high enable (bhe ) is low, then data from memory appears on io 8 to io 15 . see the truth table on page 9 for a complete description of read and write modes. for best practice recommendat ions, refer to the cypress application note an1064, sram system guidelines . logic block diagram power down circuit bhe ble ce 2 ce 1 1m 16 ram array io 0 ?io 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 io 8 ?io 15 we ble bhe a 16 a 0 a 1 a 17 a 9 a 18 a 10 ce 2 ce 1 a 19
CY62167EV18 mobl ? document #: 38-05447 rev. *e page 2 of 12 pin configuration figure 1. 48-ball vfbga (6 x 7 x 1mm) / (6 x 8 x 1mm) top view [1, 2, 3] product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( a) f = 1 mhz f = f max min typ [4] max typ [4] max typ [4] max typ [4] max CY62167EV18ll 1.65 1.8 2.25 55 2.2 4.0 25 30 1.5 12 we a 11 a 10 a 6 a 0 a 3 ce 1 io 10 io 8 io 9 a 4 a 5 io 11 io 13 io 12 io 14 io 15 v ss a 9 a 8 oe vss a 7 io 0 bhe ce 2 a 17 a 2 a 1 ble v cc io 2 io 1 io 3 io 4 io 5 io 6 io 7 a 15 a 14 a 13 a 12 a 19 a 18 nc 3 2 6 5 4 1 d e b a c f g h a 16 nc v cc notes 1. the information related to 6 x 7 x 1 mm vfbga package is preliminary. 2. nc pins are not connected on the die. 3. ball h6 for the vfbga package can be used to upgrade to a 32m density. 4. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25c.
CY62167EV18 mobl ? document #: 38-05447 rev. *e page 3 of 12 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................................ ?65c to + 150c ambient temperature with power applied ........................... ................ ?55c to + 125c supply voltage to ground potential .......................... ?0.2v to 2.45v (v cc (max) + 0.2v) dc voltage applied to outputs in high z state [5, 6] ........... ?0.2v to 2.45v (v cc (max) + 0.2v) dc input voltage [5, 6] ....... ?0.2v to 2.45v (v cc (max) + 0.2v) output current into outputs (l ow) ............................ 20 ma static discharge voltage........................................... >2001v (mil-std-883, method 3015) latch up current...................................................... >200 ma operating range device range ambient temperature v cc [7] CY62167EV18ll industrial ?40c to +85c 1.65v to 2.25v electrical characteristics over the operating range parameter description test conditions 55 ns unit min typ [4] max v oh output high voltage i oh = ?0.1 ma 1.4 v v ol output low voltage i ol = 0.1 ma 0.2 v v ih input high voltage v cc = 1.65v to 2.25v 1.4 v cc + 0.2v v v il input low voltage v cc = 1.65v to 2.25v ?0.2 0.4 v i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc (max) i out = 0 ma cmos levels 25 30 ma f = 1 mhz 2.2 4.0 ma i sb1 automatic ce power down current ? cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v v in > v cc ? 0.2v, v in < 0.2v) f = f max (address and data only), f = 0 (oe , we , bhe and ble ), v cc = v cc (max) 1.5 12 a i sb2 [8] automatic ce power down current ? cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = v cc (max) 1.5 12 a capacitance tested initially and after any design or proce ss changes that may affect these parameters. parameter description test conditions max unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf notes 5. v il (min) = ?2.0v for pulse durations less than 20 ns. 6. v ih (max) = v cc + 0.75v for pulse durations less than 20 ns. 7. full device ac operation is based on a 100 s ramp time from 0 to v cc (min) and 200 s wait time after v cc stabilization. 8. only chip enables (ce 1 and ce 2 ), and byte enables (bhe and ble ) must be tied to cmos levels to meet the i sb2 / i ccdr spec. other inputs can be left floating.
CY62167EV18 mobl ? document #: 38-05447 rev. *e page 4 of 12 thermal resistance tested initially and after any design or proce ss changes that may affect these parameters. parameter description test conditions vfbga (6 x 7 x 1mm) vfbga (6 x 8 x 1mm) unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 27.74 55 c/w jc thermal resistance (junction to case) 9.84 16 c/w ac test loads and waveforms parameters 1.8v unit r1 13500 ? r2 10800 ? r th 6000 ? v th 0.80 v data retention characteristics over the operating range parameter descripti on conditions min typ [4] max unit v dr v cc for data retention 1.0 v i ccdr [8] data retention current v cc = 1.0v, ce 1 > v cc ? 0.2v, ce 2 < 0.2v, v in > v cc ? 0.2v or v in < 0.2v 10 a t cdr [9] chip deselect to data retention time 0ns t r [10] operation recovery time t rc ns data retention waveform v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thvenin equivalent all input pulses r th r1 notes 9. tested initially and after any design or proce ss changes that may affect these parameters. 10. full device operation requires linear v cc ramp from v dr to v cc (min) > 100 s or stable at v cc (min) > 100 s. 11. bhe .ble is the and of both bhe and ble . deselect the chip by either disabling the chip enable signals or by disabling both bhe and ble . v cc (min) v cc (min) t cdr v dr > 1.0 v data retention mode t r ce 1 or v cc bhe . ble ce 2 or [11]
CY62167EV18 mobl ? document #: 38-05447 rev. *e page 5 of 12 switching characteristics over the operating range [12, 13] parameter description 55 ns unit min max read cycle t rc read cycle time 55 ns t aa address to data valid 55 ns t oha data hold from address change 10 ns t ace ce 1 low and ce 2 high to data valid 55 ns t doe oe low to data valid 25 ns t lzoe oe low to low-z [14] 5ns t hzoe oe high to high-z [14, 15] 18 ns t lzce ce 1 low and ce 2 high to low-z [14] 10 ns t hzce ce 1 high and ce 2 low to high-z [14, 15] 18 ns t pu ce 1 low and ce 2 high to power up 0 ns t pd ce 1 high and ce 2 low to power down 55 ns t dbe ble/bhe low to data valid 55 ns t lzbe ble /bhe low to low-z [14] 10 ns t hzbe ble /bhe high to high-z [14, 15] 18 ns write cycle [16] t wc write cycle time 55 ns t sce ce 1 low and ce 2 high to write end 40 ns t aw address setup to write end 40 ns t ha address hold from write end 0 ns t sa address setup to write start 0 ns t pwe we pulse width 40 ns t bw ble /bhe low to write end 40 ns t sd data setup to write end 25 ns t hd data hold from write end 0 ns t hzwe we low to high-z [14, 15] 20 ns t lzwe we high to low-z [14] 10 ns notes 12. test conditions for all parameters other than tri-state para meters are based on signal transition time of 1v/ns, timing refe rence levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in ac test loads and waveforms on page 4 . 13. ac timing parameters are subject to byte enable signals (bhe or ble ) not switching when chip is disabled. see application note an13842 for further clarification. 14. at any given temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 15. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the output enters a high impedance state. 16. the internal memory write time is defined by the overlap of we , ce 1 = v il , bhe and/or ble = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenced to the ed ge of the signal that terminates the write.
CY62167EV18 mobl ? document #: 38-05447 rev. *e page 6 of 12 switching waveforms figure 2 shows address transition co ntrolled read cy cle waveforms. [17, 18] figure 2. read cycle no. 1 figure 3 shows oe controlled read cycle waveforms. [18, 19] figure 3. read cycle no. 2 previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzbe t lzbe t hzce t dbe oe ce 1 address ce 2 bhe /ble data out v cc supply current high i cc i sb impedance notes 17. the device is continuously selected. oe , ce 1 = v il , bhe , ble or both = v il , and ce 2 = v ih . 18. we is high for read cycle. 19. address valid before or similar to ce 1 , bhe , ble transition low and ce 2 transition high.
CY62167EV18 mobl ? document #: 38-05447 rev. *e page 7 of 12 figure 4 shows we controlled write cycle waveforms. [16, 20, 21] figure 4. write cycle no. 1 switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data t bw note 22 ce 1 address ce 2 we data io oe bhe /ble notes 20. data io is high impedance if oe = v ih . 21. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 22. during this period the ios are in output state. do not apply input signals.
CY62167EV18 mobl ? document #: 38-05447 rev. *e page 8 of 12 figure 5 shows ce 1 or ce 2 controlled write cycle waveforms. [16, 20, 21] figure 5. write cycle no. 2 figure 6 shows we controlled, oe low write cycle waveforms. [21] figure 6. write cycle no. 3 switching waveforms (continued) t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data t bw t sa note 22 ce 1 address ce 2 we data io oe bhe /ble valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 22 ce 1 address ce 2 we data io bhe /ble
CY62167EV18 mobl ? document #: 38-05447 rev. *e page 9 of 12 figure 7 shows bhe /ble controlled, oe low write cycle waveforms. [21] figure 7. write cycle no. 4 truth table ce 1 ce 2 we oe bhe ble inputs/outputs mode power hxxxxxhigh z deselect / power down st andby (i sb ) xlxxxxhigh z deselect / power down st andby (i sb ) xxxxhhhigh z deselect / power down st andby (i sb ) l h h l l l data out (io 0 ?io 15 ) read active (i cc ) l h h l h l data out (io 0 ?io 7 ); high z (io 8 ?io 15 ) read active (i cc ) lhhllhhigh z (io 0 ?io 7 ); data out (io 8 ?io 15 ) read active (i cc ) l h h h l h high z output disabled active (i cc ) lhhhhlhigh z output disabled active (i cc ) l h h h l l high z output disabled active (i cc ) l h l x l l data in (io 0 ?io 15 ) write active (i cc ) l h l x h l data in (io 0 ?io 7 ); high z (io 8 ?io 15 ) write active (i cc ) lhlxlhhigh z (io 0 ?io 7 ); data in (io 8 ?io 15 ) write active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 55 CY62167EV18ll-55baxi 001-13297 48-ball vfbga (6 7 1 mm) (pb-free) industrial CY62167EV18ll-55bvxi 51- 85150 48-ball vfbga (6 8 1 mm) (pb-free) switching waveforms (continued) t hd t sd t sa t ha t aw t wc valid data t bw t sce t pwe note 22 ce 1 address ce 2 we data io bhe /ble
CY62167EV18 mobl ? document #: 38-05447 rev. *e page 10 of 12 package diagram figure 8. 48-ball vfbga (6 x 7 x 1 mm), 001-13297 notes: 1. all dimension are in mm [max/min] 2. jedec reference : mo-216 3. package weight : 0.03g 001-13297-*a
CY62167EV18 mobl ? document #: 38-05447 rev. *e page 11 of 12 figure 9. 48-ball vfbga (6 x 8 x 1 mm), 51-85150 package diagram a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.10 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 8.000.10 a 8.000.10 6.000.10 b 1.875 2.625 0.26 max. 51-85150-*d
document #: 38-05447 rev. *e re vised august 16, 2007 page 12 of 12 mobl is a registered trademark and more battery life is a trademark of cypress semiconductor. all product and company names men tioned in this document are the trademarks of their respective holders. CY62167EV18 mobl ? ? cypress semiconductor corporation, 2004-2007. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reas onably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or impl ied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress re serves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page document title: CY62167EV18 mobl ? 16-mbit (1m x 16) static ram document number: 38-05447 rev. ecn no. issue date orig. of change description of change ** 202600 01/23/04 aju new data sheet *a 463674 see ecn nxr converted from ad vance information to preliminary changed v cc(max) from 2.20v to 2.25v removed ?l? bin and 35 ns speed bin from product offering changed ball e3 from dnu to nc removed redundant foot note on dnu changed the i sb2(typ) value from 1.3 a to 1.5 a changed the i cc(max) value from 40 ma to 25 ma changed the ac test load capacitance value from 50 pf to 30 pf corrected typo in data retention characteristics (t r ) from 100 s to t rc ns changed the i ccdr value from 8 a to 5 a changed t oha , t lzce , t lzbe , and t lzwe from 6 ns to 10 ns changed t lzoe from 3 ns to 5 ns changed t hzoe , t hzce , t hzbe , and t hzwe from 15 ns to 18 ns changed t sce , t aw , and t bw from 40 ns to 35 ns changed t pe from 30 ns to 35 ns changed t sd from 20 ns to 25 ns updated 48 ball fbga package information updated the ordering information table *b 469182 see ecn nsi minor change: moved to external web *c 619122 see ecn nxr replaced 45 ns speed bin with 55 ns speed bin *d 1130323 see ecn vkn converted from preliminary to final added footnote# 8 related i sb2 and i ccdr changed i sb1 and i sb2 spec from 10 a to 12 a changed i ccdr spec from 8 a to 10 a added footnote# 13 related ac timing parameters changed t wc spec from 45 ns to 55 ns changed t sce , t aw , t pwe , t bw spec from 35 ns to 40 ns changed t hzwe spec from 18 ns to 20 ns *e 1388287 see ecn vkn added 48-ball vfbga (6 x 7 x 1mm) package added footnote# 1 related to fbga package updated ordering information table

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